AI-server power is no longer a market in which one IC can win the entire design. At one end sits an 800 V high-voltage DC bus. At the other, a GPU core may need hundreds of amperes at roughly 1 V. Between them are a 48 V intermediate bus, DCX stages, eFuses, point-of-load converters and multiphase VRMs. A weak link anywhere in that chain can force an expensive accelerator to throttle.
Chipown's 2026 interim report says more than ten products for AI-computing power have entered production in succession. The list spans a 1700 V SiC auxiliary supply, isolated and SiC/GaN gate drivers, megahertz-class DCX controllers, 8-, 12- and 16-phase VRMs, 70 A and 90 A Cu-Clip DrMOS, eFuses and POL converters. That is a step beyond a product announcement: the devices have moved beyond laboratory demonstration.
"Entered production" does not establish adoption by a named AI-server customer, and it does not prove material revenue. The report does not disclose every part number, customer, shipment or revenue contribution. The more important question is why Chipown is assembling a complete power chain instead of betting on one flagship IC.
1. The objective is the power chain, not the product count
Chipown's public AI-data-center architecture can be divided into three levels. On the high-voltage side, PN8703 is a 1700 V integrated AC-DC device intended for auxiliary conversion in an 800 V HVDC system. Isolated and SiC/GaN drivers control the high-voltage power switches. At the intermediate bus, the PN6867 full-bridge DC/DC controller, the PN6869 DCX controller operating at up to 1.5 MHz, and PN7893/PN788X eFuses handle conversion and branch protection around the 48 V domain.
The final stage, closest to the GPU or CPU, uses PN68XX multiphase controllers, PN786X DrMOS and PN6850/PN6851 POL devices. The controller schedules phases, the DrMOS stages move the high current, the eFuse manages hot-plug and fault isolation, and the POL devices feed memory, interfaces and other peripheral rails. Chipown is not simply selling a collection of unrelated chips; it is building a set of power blocks that reaches from an 800 V bus to a 1 V core rail.
A platform approach can reduce cross-vendor tuning. When the controller, power stage and protection devices come from different suppliers, engineers must reconcile current-sense gain, temperature reporting, dead time, protection thresholds and telemetry accuracy. A coordinated portfolio can shorten that work, but one-vendor availability is only a starting point. The complete system still requires platform, thermal, firmware and lot validation.
2. Sixteen phases and 90 A look impressive, but the numbers must work together
Chipown lists several concrete controllers. PN6835 is an eight-phase device supporting PMBus, AVSBus and SVID. PN6844 provides twelve phases for SVI3 platforms. PN6858 provides sixteen phases with PMBus and SVI3. The associated PN7864 DrMOS is rated at 70 A in a 5 x 6 mm package; PN7865 is rated at 90 A in the same footprint; PN7866 places a 90 A capability in a 4 x 6 mm package.
Those specifications put the parts into an internationally competitive parameter range. Renesas RAA228227 is an active dual-output, 16-phase controller with AVSBus, PMBus, NVM configuration and the PowerNavigator tool. TI TPS53685 is an eight-phase controller for AMD platforms supporting SVI3, PMBus, TLVR and NVM. Chipown can therefore sit at the same parameter table for phase count, protocol support and current per power stage.
But more phases are not automatically better. They share current and reduce thermal stress per phase, while increasing layout, current-balance, timing and control complexity. A 70 A or 90 A rating describes the capability of one power stage under defined conditions; it cannot be multiplied by phase count to predict accelerator-card output. Engineers ultimately need transient droop, phase-to-phase temperature spread, TLVR stability, telemetry accuracy and protection behavior.
The real threshold for a China-developed multiphase solution is not producing sixteen PWM outputs. It is making all sixteen act as one under high temperature, full load and fast transients.
3. Production is not the same as broad volume adoption
Production status shows that the products are more than engineering samples, but production, customer adoption and material revenue are separate states. Chipown reported first-half 2026 revenue of RMB 665 million, up 4.57% year on year; net profit attributable to shareholders of RMB 158 million, up 74.13%; and R&D expense of RMB 141 million, or 21.24% of revenue. These are company-wide figures and cannot be assigned to AI-server power.
The report does not identify which customers use PN6835, PN6858, PN7865 or PN7893, nor does it disclose AI-server sales, shipments, yield or revenue share. It supports the statement that more than ten products have progressively entered production. It does not support a claim that the portfolio is already in high-volume BOMs at a particular GPU vendor, server ODM or cloud operator.
Chipown also describes PN68XX devices as pin-to-pin alternatives to mainstream competitors without publishing a complete mapping of competitor part numbers. Procurement teams should not translate a family-level statement into "solder it down and it works." Even when pin locations match, compensation, sequencing, NVM settings, fault registers, telemetry gain, exposed-pad thermals and software tools may differ. Pin compatibility can save layout time; it cannot eliminate platform validation.
4. How should a China-based AI-power platform be introduced?
Start with processor protocol. SVI2, SVI3, SVID, AVSBus and proprietary interfaces are not interchangeable languages. The controller's ability to communicate correctly with the target CPU, GPU or ASIC determines whether the project can start long before maximum phase count matters. The next validation set covers load steps, current-sharing error, overcurrent behavior, thermal shutdown, PMBus telemetry and full-temperature stability.
Power and thermal design form a second track. PN7864, PN7865 and PN7866 current ratings must be evaluated with input voltage, switching frequency, PCB copper, airflow or liquid cooling. An eFuse requires safe-operating-area, short-circuit shutdown, latch-versus-hiccup behavior and hot-plug testing—not just a 30 A or 60 A label. At the 800 V HVDC stage, isolation, surge, EMC, SiC/GaN gate-drive behavior and safe failure modes create an entirely different qualification program.
A practical adoption path validates peripheral POL and eFuse functions alongside the core VRM on a new platform, while maintaining a separate high-voltage path for the auxiliary supply, DCX and isolated drivers. Procurement should obtain evaluation hardware, configuration tools, complete data sheets, errata, a PCN process, lot traceability and long-term supply commitments. A second source and a rollback path remain necessary.
A lower chip price does not guarantee a lower migration cost. If the controller, DrMOS, eFuse and POL devices can be debugged as one platform, however, the savings may extend beyond component cost to engineering time, inventory and multi-vendor coordination.
Conclusion
Chipown's portfolio shows how the competitive frame for China-based power IC suppliers is changing. Winning one socket is useful; supporting the full chain from 800 V auxiliary conversion to a 1 V core rail can create a platform relationship.
The remaining test is evidence. The market needs customer-level qualification, platform compatibility, transient and thermal data, production consistency, software-tool maturity and repeatable delivery. Until those elements are visible, the right description is "a broad portfolio entering production," not "a complete AI-server platform already deployed at scale."
Disclaimer: This article is based on public information and is for industry discussion only. It is not investment, procurement or part-selection advice. Confirm specifications, production status, customer adoption and supply information with the manufacturer and project owner.
